Modern Digital Designs With Eda Vhdl And Fpga Pdf

architecture rtl of simple_axi_reg is signal reg0 : std_logic_vector(31 downto 0) := (others => '0'); begin process(clk) begin if rising_edge(clk) then if resetn = '0' then reg0 <= (others => '0'); elsif s_axi_awvalid and s_axi_wvalid then reg0 <= s_axi_wdata; end if; end if; end process; end architecture;

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Note: This shows a synthesizable, ready-to-use AXI-lite write register. architecture rtl of simple_axi_reg is signal reg0 :