Synopsys Design Compiler Tutorial -

compile_ultra # strongly recommended over old "compile"

If a signal takes 3 clock cycles to compute, tell DC: synopsys design compiler tutorial

set_max_fanout 20 [current_design] set_max_capacitance 0.5 [current_design] Use code with caution. Step 4: Compile (The Magic Step) compile_ultra # strongly recommended over old "compile" If

If you give me your and design type (CPU, DSP, controller) , I can tailor the constraint values and optimization switches further. synopsys design compiler tutorial