endmodule
| Option | Setting | |--------|---------| | Component Name | dds_1MHz_example | | Output Selection | Sine (only) | | Phase Increment Programmability | Fixed (to save resources) | | Phase Offset Programmability | None | | Output Width | 12 bits (common for low-cost DACs) | | Phase Width (Accumulator) | 32 bits | Dds Compiler 6.0 Example
Choose "Hardware Parameters" for manual control over bit widths or "System Parameters" to let the tool calculate widths based on SFDR requirements. Phase Width: Set to 32 bits. endmodule | Option | Setting | |--------|---------| |
This formula is the key to programming the DDS dynamically. If the accumulator width is 24 bits and the clock is 100 MHz, calculating the hex value for a 5 MHz sine wave requires plugging these numbers into the formula, which we will do in our example. If the accumulator width is 24 bits and
To verify the DDS works, we run a simulation. Below is a simple testbench in Verilog.
Last updated: May 2026 – Compatible with Vivado 2023.2 and newer.