| Function | Original behavior | |----------|------------------| | | 256×192 pixels, 15 colors, 8×8 attribute cells, 50/60 Hz interlaced (later progressive) | | CPU wait states | Contended memory access for video reads | | DRAM refresh | RAS/CAS generation, refresh counter | | Keyboard | 8×5 matrix, read via port $xxFE | | Tape I/O | Edge detection for loading, bit-banged output | | Sound | 1-bit beeper toggling | | Border | Color border controlled by port $xxFE |
The Z80 CPU runs at 3.5MHz. The ULA needs to access the DRAM at 7MHz (twice as fast). Why? Because for every pixel drawn, the ULA must fetch both the pixel bitmap and the colour attribute. Because for every pixel drawn, the ULA must
The ZX Spectrum ULA is a case study in "Engineering on the edge." Ferranti’s ULA technology was notorious for long lead times and high minimum orders. Sinclair bet the company on it. When the first ULAs arrived faulty, production almost stopped. When the first ULAs arrived faulty, production almost
Use dual-port SRAM or fast DRAM with a small state machine in the FPGA. Avoid original DRAM’s 2-4ms refresh – use static RAM. When the first ULAs arrived faulty
Spectrum uses a minimal I/O map:
The ULA acted as a "gatekeeper." It used a 14MHz clock internally, divided down.