Sd3.0-host-ahb-emmc4.4-usersguide-ver5.9-jan11-10.pdf __link__ -

// Set AHB clock to 66 MHz, divide by 2 for host core (33 MHz) write_register(SDCTL, (1 << 8) | 0x01); // Soft reset | Clock div 2 delay_ms(10);

– eMMC 4.4 uses DS for DDR modes; the guide warns about routing DS separately from CLK – a common layout mistake. sd3.0-host-ahb-emmc4.4-usersguide-ver5.9-jan11-10.pdf